Integrated circuits (ICs) may be damaged from electrostatic discharge (ESD) when a source of electrostatic potential (e.g., human body) comes to contact with the integrated circuits, as an ESD spike may show up, with a voltage reaching up to several thousand volts within a very short time period, typically within 10-100 ns.
An ESD protection circuit is often placed between a first node and a second node to protect an integrated circuit coupled therebetween against an ESD event. Conventional Grounded Gate NMOS (GGNMOS) architecture is a frequent choice for an ESD protection circuit. In such architecture, the drain of an NMOS transistor is coupled to the first node, while the source and gate of the NMOS transistor are coupled to the second node. Additionally coupled to the second node is the body of the NMOS transistor. When an ESD spike shows up at the first node, the parasitic bipolar transistor formed by the drain, the body and the source of the NMOS transistor is turned on and conducts current from the first node to the second node to discharge ESD energy, due to the reverse junction breakdown and secondary breakdown of the parasitic bipolar transistor, which is observed as a snapback behavior. See, for example, H. Sarbishaei, Electrostatic Discharge Protection Circuit for High-Speed Mixed-Signal Circuits, pp. 17-20, (PHD thesis to Waterloo), which is incorporated herein by reference.
However, one drawback with such GGNMOS configuration is that when a noise is coupled to the second node, with a voltage value which makes the difference between the noise voltage and the voltage at the first node higher than the forward on-threshold voltage of the drain-body junction of the parasitic bipolar transistor, such drain-body junction is forward biased and is turned on. And consequently, the drain voltage, i.e., the voltage at the first node which is supplied to the integrated circuit follows the noise voltage, introducing the possibility of disturbing the integrated circuit through noise sensitivity of any circuitry connected to the second node.
Thus, there is a need for addressing these and/or other issues associated with this conventional GGNMOS ESD protection circuit.